JEDEC (Joint Electron Device Engineering Council) promulgates several standards including the UFS standard for high performance mobile storage devices. The UFS has adopted MIPI (Mobile Industry Processor Interface) for data transfer in mobile systems. The UFS is a standard to provide high-performance serial interface for moving data between a host and a storage device.
FIG. 1 illustrates a conventional UFS system that includes a UFS host 110 and a UFS device 170 configured to communicate with each other over a lane. The UFS host 110 includes a UFS host controller 115, and the UFS device 170 includes a RAM (random access memory) 185 and a flash memory 195. In FIG. 1, operations represented by circled numbers (1) and (2) represent a typical command-response communication sequence between the UFS host 110 and the UFS device 170. For example, operation (1) may be a command (e.g., read, write), and operation (2) may be a response (e.g., success or failure) to the command.
When accessing the UFS device 170 for read and write, the UFS host controller 115 issues the command based on an LBA (logical block address) associated with the UFS device 170. For example, (1) may be in a form of “command (LBA=a)”. The UFS device 170 performs an L2P (logical-to-physical) mapping to find a PBA (physical block address) corresponding to the given LBA, then accesses the physical memory location of the flash memory 195 to service the command.
The entire L2P map for the UFS device 170 is in the flash memory 195. However, to enable faster mapping, the L2P map can be stored in the RAM 185. A typical ratio between the L2P map and the total storage capacity is 1:1000. For example, if the storage capacity of the UFS device 170 (e.g., capacity of the flash memory 195) is 256 GB, then to store the entire L2P map in the RAM 185, the RAM 185 should have a 256 MB capacity. Unfortunately, a typical UFS device has a limited amount of SRAM (e.g., 1-2 MB). Thus, only a portion of the L2P map is stored in the RAM 185.
If the received command specifies an LBA that belongs to the L2P map portion in the RAM 185 (e.g., if LBA=a), the corresponding PBA (e.g., PBA=A) can be found relatively quickly. However, if the received command has an LBA that does not belong to the L2P map portion currently in the RAM 185 (e.g., if LBA=c), the missing L2P map portion is read from the flash memory 195, and then the corresponding PBA (e.g., PBA=C) is found. This can lead to significant performance impact whenever the received LBA is not in the RAM 185. The problem can be especially acute when the RAM 185 is very small compared to the flash memory 195 since it is more likely that the received LBA will not be in the RAM 185.